In a synchronous integrated circuit (IC), clock signals are used to define a time reference for the movement of data within the circuit. The IC's clock distribution network (e.g., clock generation circuitry, wiring, buffering and registers) generates clock signals and distributes them from a particular point to all of the circuit elements that need them. The performance of a synchronous IC heavily depends on its clock distribution network design. The proper design of the clock distribution network helps ensure that critical timing requirements are satisfied and that clock skew is controlled. As IC's become larger, their clock distribution networks start to take up large portions of the design resources. Clock signals typically have the greatest fan-out and have to operate at the highest speeds of any control or data signal within the entire design. Clock power is typically more than one-third of total power consumption of a typical IC and is due to (i) clock tree wiring, (ii) clock tree buffers and (iii) clock tree sinks (e.g., flip-flops). Therefore, developing a scalable, high-speed, high-performance and low-power clock distribution network design is extremely difficult given the existing skew/slew constraints in large IC's.
3D IC's is an emerging technology that can provide higher-performance/lower-power designs. However, known 3D IC implementations tend to exacerbate clock distribution network design challenges because the clock signal has to reliably span across multiple tiers under tight skew/slew constraints. Hence, different tiers will have their own clock tree network. It is also impossible to meet skew/slew constraints across different clock networks spanning different tiers without degrading performance and power. To cope with this problem, asynchronous operation at the chip level is required, which then has its own disadvantages in various parameters including power consumption, speed and area footprint.
Accordingly, there is a need for systems and methods for developing clock distribution networks that are scalable, low-skew, high-speed and high-performance. There is a further need for systems and methods for developing clock distribution networks that are scalable, low-skew, high-speed and high-performance, within a 3D IC.